Instruction Set Architecture

Hardwired encoding

Type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Jumps negate condition2 condition1 condition0
Moves source2 source1 source0 destination2 destination1 destination0
ALU ops carry1 carry0 source2 source1 source0 function2 function1 function0
Shifts direction

The encoded values
Value Function Condition Src./Dest. Carry Negate Direction
0 0x00 Sign r0 No carry Unchanged Shift Left
1 B - A Zero r1 No carry Negate Shift Right
2 A - B Overflow r2 No carry
3 A + B Carry r3 Use carry
4 A xor B Aux. carry r4
5 A or B (reserved) r5
6 A and B (reserved) r6
7 0xFF (reserved) r7

Instruction table

Each color represents an instruction group, where every instruction is identical to the Control Unit.
The bits in the opcode itself determine the exact effect the instruction has.
See tables above for opcode encoding.
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HEX OCTAL xx0 xx1 xx2 xx3 xx4 xx5 xx6 xx7 HEX OCTAL xx0 xx1 xx2 xx3 xx4 xx5 xx6 xx7 SRC
00 00x NOP HLT CLI SEI RETI 80 20x ST
r0, a16
CMP
r0
SUB
r0
ADD
r0
XOR
r0
OR
r0
AND
r0
OUT
r0, a16
r0
08 01x JMPS
a16
JMPZ
a16
JMPV
a16
JMPC
a16
JMPA
a16
CALL
a16
RET JMP
a16
88 21x ST
r1, a16
CMP
r1
SUB
r1
ADD
r1
XOR
r1
OR
r1
AND
r1
OUT
r1, a16
r1
10 02x JMPNS
a16
JMPNZ
a16
JMPNV
a16
JMPNC
a16
JMPNA
a16
90 22x ST
r2, a16
CMP
r2
SUB
r2
ADD
r2
XOR
r2
OR
r2
AND
r2
OUT
r2, a16
r2
18 03x 98 23x ST
r3, a16
CMP
r3
SUB
r3
ADD
r3
XOR
r3
OR
r3
AND
r3
OUT
r3, a16
r3
18 04x POP
r0
POP
r1
POP
r2
POP
r3
POP
r4
POP
r5
POP
r6
POP
r7
A0 24x ST
r4, a16
CMP
r4
SUB
r4
ADD
r4
XOR
r4
OR
r4
AND
r4
OUT
r4, a16
r4
28 05x LDI
d8, r0
LDI
d8, r1
LDI
d8, r2
LDI
d8, r3
LDI
d8, r4
LDI
d8, r5
LDI
d8, r6
LDI
d8, r7
A8 25x ST
r5, a16
CMP
r5
SUB
r5
ADD
r5
XOR
r5
OR
r5
AND
r5
OUT
r5, a16
r5
18 06x LD
a16, r0
LD
a16, r1
LD
a16, r2
LD
a16, r3
LD
a16, r4
LD
a16, r5
LD
a16, r6
LD
a16, r7
B0 26x ST
r6, a16
CMP
r6
SUB
r6
ADD
r6
XOR
r6
OR
r6
AND
r6
OUT
r6, a16
r6
38 07x IN
a16, r0
IN
a16, r1
IN
a16, r2
IN
a16, r3
IN
a16, r4
IN
a16, r5
IN
a16, r6
IN
a16, r7
B8 27x ST
r7, a16
CMP
r7
SUB
r7
ADD
r7
XOR
r7
OR
r7
AND
r7
OUT
r7, a16
r7
40 10x MOV
r0, r0
MOV
r0, r1
MOV
r0, r2
MOV
r0, r3
MOV
r0, r4
MOV
r0, r5
MOV
r0, r6
MOV
r0, r7
C0 30x PUSH
r0
CMP
d8
SBB
r0
ADC
r0
SHL
r0
SHR
r0
TST? r0
48 11x MOV
r1, r0
MOV
r1, r1
MOV
r1, r2
MOV
r1, r3
MOV
r1, r4
MOV
r1, r5
MOV
r1, r6
MOV
r1, r7
C8 31x PUSH
r1
SBB
r1
ADC
r1
SHL
r1
SHR
r1
TST? r1
50 12x MOV
r2, r0
MOV
r2, r1
MOV
r2, r2
MOV
r2, r3
MOV
r2, r4
MOV
r2, r5
MOV
r2, r6
MOV
r2, r7
D0 32x PUSH
r2
SBB
r2
ADC
r2
SHL
r2
SHR
r2
TST? r2
58 13x MOV
r3, r0
MOV
r3, r1
MOV
r3, r2
MOV
r3, r3
MOV
r3, r4
MOV
r3, r5
MOV
r3, r6
MOV
r3, r7
D8 33x PUSH
r3
SBB
r3
ADC
r3
SHL
r3
SHR
r3
TST? r3
60 14x MOV
r4, r0
MOV
r4, r1
MOV
r4, r2
MOV
r4, r3
MOV
r4, r4
MOV
r4, r5
MOV
r4, r6
MOV
r4, r7
E0 34x PUSH
r4
SBB
r4
ADC
r4
SHL
r4
SHR
r4
TST? r4
68 15x MOV
r5, r0
MOV
r5, r1
MOV
r5, r2
MOV
r5, r3
MOV
r5, r4
MOV
r5, r5
MOV
r5, r6
MOV
r5, r7
E8 35x PUSH
r5
SBB
r5
ADC
r5
SHL
r5
SHR
r5
TST? r5
70 16x MOV
r6, r0
MOV
r6, r1
MOV
r6, r2
MOV
r6, r3
MOV
r6, r4
MOV
r6, r5
MOV
r6, r6
MOV
r6, r7
F0 36x PUSH
r6
SBB
r6
ADC
r6
SHL
r6
SHR
r6
TST? r6
78 17x MOV
r7, r0
MOV
r7, r1
MOV
r7, r2
MOV
r7, r3
MOV
r7, r4
MOV
r7, r5
MOV
r7, r6
MOV
r7, r7
F8 37x PUSH
r7
SBB
r7
ADC
r7
SHL
r7
SHR
r7
TST? r7
DST r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7
ALU 0x00 B - A A - B A + B A xor B A or B A and B 0xFF 0x00 B - A A - B A + B A xor B A or B A and B 0xFF