Architecture

The Zora CPU has an 8bit databus and 16bit address bus, meaning it can address up to 64k of RAM.
It has no memory managament unit, and thus virtual memory is not supported in hardware.

Details:

Overview




ALU

The ALU is built around two Am25LS2517 4-bit bitslice ALUs.
It takes two 8bit inputs (A and B in the diagram), and outputs an 8bit result based on the selected operation (the Op input) to the databus (the unlabeled output). During the calculation, it will also generate some condition flags which are fed to the Flags out output, to be stored in the FLAG register for some instructions. The flag bits are: